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Chapter 3: Functional Description
Device-Level Description
Figure 3–9. Stratix PLL Configuration
Stratix De v ice
(Note 1)
3–15
Stratix DLL
DDR SDRAM
dqs_ref_clk
C0
C1
clk
write_clk
Controller
altddio
altddio
clk_to_sdram
clock_source
Enhanced PLL
C2
resynch_clk or
capture_clk
altddio
clk_to_sdram_n
DDR SDRAM
C3
postamble_clk
Note 1
Note to Figure 3–9 :
(1) In most cases, clk or write_clk are used as the resynchronization and postamble clocks, therefore you need not use a separate clock output
from the PLL.
Figure 3–10 shows the Cyclone II configuration for use with any PLL multiply or
divide ratios including a ratio of one.
Figure 3–10. Cyclone II PLL Configuration
Cyclone II De v ice
DDR SDRAM
Controller
clock_source
PLL
C0
C1
C2
clk
write_clk
resynch_clk
altddio
altddio
clk_to_sdram
clk_to_sdram_n
DDR SDRAM
Figure 3–11 on page 3–15 shows the Cyclone configuration.
Figure 3–11. Cyclone PLL Configuration
Cyclone De v ice
DDR SDRAM
Controller
clock_source
PLL
C0
C1
clk
write_clk
altddio
clk_to_sdram
clk_to_sdram_n
DDR SDRAM
altddio
? March 2009
Altera Corporation
DDR and DDR2 SDRAM Controller Compiler User Guide
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